Dajiang LIU

Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral Optimizations
Dajiang LIU Shouyi YIN Leibo LIU Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1419-1430
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
coarse-grained reconfigurable architecture, loops, polyhedral model, mapping, 
 Summary | Full Text:PDF
Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs
Shouyi YIN Dajiang LIU Leibo LIU Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1582-1591
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
reconfigurable computing, loop transformation, polyhedra model, compiling, 
 Summary | Full Text:PDF
Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture
Dajiang LIU Shouyi YIN Chongyong YIN Leibo LIU Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12  pp. 2898-2907
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer Architecture
Keyword: 
reconfigurable computing, affine loop, polyhedron model, parallel computing, 
 Summary | Full Text:PDF