IEICE Trans

Daisuke SUZUKI

Adversarial Black-Box Attacks with Timing Side-Channel Leakage Tsunato NAKAI Daisuke SUZUKI Fumio OMATSU Takeshi FUJINO
Publication: Publication Date: 2021/01/01 Vol. E104-A No. 1 pp. 143-151 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Keyword: adversarial example, deep neural network, side-channel attack, timing attack, black-box attack,
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Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme Daisuke SUZUKI Takahiro HANYU
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 pp. 1618-1624 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: VLSI Architecture Keyword: field-programmable gate array (FPGA), power gating, magnetic tunnel junction (MTJ) device, and low power digital,
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Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack Takeshi SUGAWARA Daisuke SUZUKI Minoru SAEKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1323-1333 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: RSA, side-channel attack, collision attack, Montgomery multiplication,
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Faster Enumeration of All Maximal Cliques in Unit Disk Graphs Using Geometric Structure Taisuke IZUMI Daisuke SUZUKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/03/01 Vol. E98-D No. 3 pp. 490-496 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science---New Spirits in Theory of Computation and Algorithm---) Category: Keyword: enumerating maximal cliques, Bron-Kerbosch algorithm, Unit disk graph,
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Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication Koichi SHIMIZU Daisuke SUZUKI Toyohiro TSURUMARU Takeshi SUGAWARA Mitsuru SHIOZAKI Takeshi FUJINO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/01/01 Vol. E97-A No. 1 pp. 264-274 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Hardware Based Security Keyword: Physical Unclonable Function, PUF, Glitch PUF, Physical Random Number Generator, Spartan-3A, Spartan-6,
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Metastable Ordered Phase Formation in CoPt and Co₃Pt Alloy Thin Films Epitaxially Grown on Single-Crystal Substrates Mitsuru OHTAKE Daisuke SUZUKI Fumiyoshi KIRINO Masaaki FUTAMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/12/01 Vol. E96-C No. 12 pp. 1460-1468 Type of Manuscript: REVIEW PAPER Category: Keyword: CoPt, Co₃Pt, metastable ordered phase, epitaxial thin film growth, perpendicular magnetic anisotropy,
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Glitch PUF: Extracting Information from Usually Unwanted Glitches Koichi SHIMIZU Daisuke SUZUKI Tomomi KASUYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/01/01 Vol. E95-A No. 1 pp. 223-233 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: physical unclonable function, PUF, Glitch, delay,
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How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation Daisuke SUZUKI Tsutomu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 pp. 211-222 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: hardware architecture, modular exponentiation, Montgomery multiplication, FPGA, DSP,
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How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers Daisuke SUZUKI Minoru SAEKI Koichi SHIMIZU Tsutomu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 pp. 200-210 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: hardware architecture, differential power analysis, correlation power analysis, template attack,
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A Design Methodology for a DPA-Resistant Circuit with RSL Techniques Daisuke SUZUKI Minoru SAEKI Koichi SHIMIZU Akashi SATOH Tsutomu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2497-2508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: side-channel attacks, differential power analysis, hardware countermeasure, random switching logic, CMOS logic circuit,
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Increasing the Strength of Odors Produced by an Odor-Emitting Technology Using Odor Capsules Ayako NISHIMURA Minoru SAKAIRI Daisuke SUZUKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/04/01 Vol. E93-D No. 4 pp. 903-908 Type of Manuscript: PAPER Category: Multimedia Pattern Processing Keyword: odor-emitting apparatus, multi-valve sequence mode, odor capsule, back seat of an automobile,
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High-Speed Passphrase Search System for PGP Koichi SHIMIZU Daisuke SUZUKI Toyohiro TSURUMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/01/01 Vol. E93-A No. 1 pp. 202-209 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Application Keyword: passphrase, search, FPGA, PGP, security,
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Olfaction Presentation System Using Odor Scanner and Odor-Emitting Apparatus Coupled with Chemical Capsules of Alginic Acid Polymer Minoru SAKAIRI Ayako NISHIMURA Daisuke SUZUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/02/01 Vol. E92-A No. 2 pp. 618-629 Type of Manuscript: PAPER Category: General Fundamentals and Boundaries Keyword: olfaction presentation system, odor-emitting apparatus, odor scanner, chemical capsule,
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Security Evaluations of MRSL and DRSL Considering Signal Delays Minoru SAEKI Daisuke SUZUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 pp. 176-183 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Side Channel Attacks Keyword: DPA, data masking, dual-rail circuit, countermeasure, hardware, RSL, MRSL, DRSL,
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An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style Daisuke SUZUKI Minoru SAEKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 pp. 184-192 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Side Channel Attacks Keyword: side-channel attacks, differential power analysis, hardware countermeasure, dual-rail pre-charge logic style, CMOS logic circuit,
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Pulse-Width Modulation with Current Uniformization for TFT-OLEDs Mutsumi KIMURA Shigeki SAWAMURA Masakazu KATO Yuji HARA Daisuke SUZUKI Hiroyuki HARA Satoshi INOUE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/11/01 Vol. E90-C No. 11 pp. 2076-2082 Type of Manuscript: INVITED PAPER (Special Section on Electronic Displays) Category: Keyword: pulse-width modulation, current uniformization, TFT-OLED, circuit simulation, characteristic compensation, luminance uniformity,
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Leakage Analysis of DPA Countermeasures at the Logic Level Minoru SAEKI Daisuke SUZUKI Tetsuya ICHIKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/01/01 Vol. E90-A No. 1 pp. 169-178 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Side Channel Attacks Keyword: side-channel attacks, differential power analysis, hardware countermeasure, CMOS logic circuit, second-order DPA,
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Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level Daisuke SUZUKI Minoru SAEKI Tetsuya ICHIKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/01/01 Vol. E90-A No. 1 pp. 160-168 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Side Channel Attacks Keyword: side-channel attacks, differential power analysis, hardware countermeasure, second-order DPA random switching logic, CMOS logic circuit,
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A New Product-Sum Type Public Key Cryptosystem Based on Reduced Bases Daisuke SUZUKI Yasuyuki MURAKAMI Ryuichi SAKAI Masao KASAHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/01/01 Vol. E84-A No. 1 pp. 326-330 Type of Manuscript: Special Section LETTER (Special Section on Cryptography and Information Security) Category: Keyword: low-density attack, product-sum type public key cryptosystems, reduced base,
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