Daisaburo TAKASHIMA


Overview and Trend of Chain FeRAM Architecture
Daisaburo TAKASHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6  pp. 747-756
Type of Manuscript:  INVITED PAPER (Special Issue on Nonvolatile Memories)
Category: FeRAMs
Keyword: 
ferroelectricnonvolatilememoryFeRAMchain FeRAM
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Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
Shinichiro SHIRATAKE Daisaburo TAKASHIMA Takehiro HASEGAWA Hiroaki NAKANO Yukihito OOWAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 573-581
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAMcascadeNANDfolded bitlineopen bitlinedie sizenoise immunity
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A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs
Tsuneo INABA Daisaburo TAKASHIMA Yukihito OOWAKI Tohru OZAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12  pp. 1699-1706
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
DRAMpower dissipationreliabilitybit-linewordlinesmall swingthreshold voltagesense amplifiermemory cell
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Open/Folded Bit-Line Arrangement for Ultra-High-Density DRAM's
Daisaburo TAKASHIMA Shigeyoshi WATANABE Hiroaki NAKANO Yukihito OOWAKI Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 869-872
Type of Manuscript:  Special Section LETTER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
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Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory
Daisaburo TAKASHIMA Shigeyoshi WATANABE Hiroaki NAKANO Yukihito OOWAKI Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 771-777
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
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Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM's
Daisaburo TAKASHIMA Shigeyoshi WATANABE Tsuneaki FUSE Kazumasa SUNOUCHI Takahiko HARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C  No. 5  pp. 844-849
Type of Manuscript:  Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
Category: 
Keyword: 
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Word-Line Architecture for Highly Reliable 64-Mb DRAM
Daisaburo TAKASHIMA Yukihito OOWAKI Ryu OGIWARA Yohji WATANABE Kenji TSUCHIDA Masako OHTA Hiroaki NAKANO Shigeyoshi WATANABE Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 501-507
Type of Manuscript:  Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
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