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Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks
Naoya TORII Dai YAMAMOTO Masahiko TAKENAKA Tsutomu MATSUMOTO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/01/01
Vol. E99-A
No. 1
pp. 118-129
Type of Manuscript:
Special Section PAPER (Special Section on Cryptography and Information Security)
Category:
Keyword:
PUF, FIB, RS-latch, | | | Summary | Full Text:PDF(2.1MB) | |
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Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher
Dai YAMAMOTO Kouichi ITOH Jun YAJIMA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12
pp. 2628-2638
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
block cipher, KASUMI, hardware, ASIC, FPGA, compact implementation, | | | Summary | Full Text:PDF(945.4KB) | |
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Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher
Dai YAMAMOTO Jun YAJIMA Kouichi ITOH | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/01/01
Vol. E93-A
No. 1
pp. 3-12
Type of Manuscript:
Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Symmetric Cryptography
Keyword:
block cipher, MISTY1, hardware, ASIC, compact implementation, | | | Summary | Full Text:PDF(599.3KB) | |
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