Chung-Yu WU

The Design of a K-Band 0.8-V 9.2-mW Phase-Locked Loop
Zue-Der HUANG Chung-Yu WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/08/01
Vol. E94-C  No. 8  pp. 1289-1294
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
phase-locked loop (PLL), VCO, coupling current-mode injection-locked frequency divider (CCMILFD), SPR-PFD, complementary-type charge pump, 
 Summary | Full Text:PDF(1.1MB)
An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications
Po-Hung CHEN Min-Chiao CHEN Chun-Lin KO Chung-Yu WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6  pp. 877-883
Type of Manuscript:  PAPER
Category: Microwaves, Millimeter-Waves
Keyword: 
V-band, transceivers, CMOS subharmonic frequency tripler, monolithic microwave integrated circuit (MMIC), 
 Summary | Full Text:PDF(942.7KB)
A Low-Power K-Band CMOS Current-Mode Up-Conversion Mixer Integrated with VCO
Wen-Chieh WANG Chung-Yu WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/10/01
Vol. E92-C  No. 10  pp. 1291-1298
Type of Manuscript:  PAPER
Category: Microwaves, Millimeter-Waves
Keyword: 
CMOS, current-mode, K-band, up-conversion mixer, 
 Summary | Full Text:PDF(1.1MB)
New Design Methodology and New Differential Logic Circuits for the Implementation of Ternary Logic Systems in CMOS VLSI without Process Modification
Hong-Yi HUANG Chung-Yu WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/06/25
Vol. E77-C  No. 6  pp. 960-969
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ternary logic system, CMOS dynamic logic circuit, binary-coded ternary signal, redundant binary adder, 
 Summary | Full Text:PDF(912KB)