Chung-Chieh KUO


Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement
Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A  No. 2  pp. 706-716
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock routingdesign for manufacturabilitydouble viaX-architecture
 Summary | Full Text:PDF

Zero-Skew Driven Buffered RLC Clock Tree Construction
Jan-Ou WU Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/03/01
Vol. E90-A  No. 3  pp. 651-658
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock treeupward propagationbuffer insertionzero skewSoC
 Summary | Full Text:PDF