Chizu MATSUMOTO


Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs
Chizu MATSUMOTO Yuichi HAMAMURA Michinobu NAKAO Kaname YAMASAKI Yoshikazu SAITO Shun'ichi KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/01/01
Vol. E96-C  No. 1  pp. 108-114
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
random access memorysystem-on-chipredundancyfuse
 Summary | Full Text:PDF

A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis
Chizu MATSUMOTO Yuichi HAMAMURA Yoshiyuki TSUNODA Hiroshi UOZAKI Isao MIYAZAKI Shiro KAMOHARA Yoshiyuki KANEKO Kenji KANAMITSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3  pp. 353-360
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
defectsfailure analysisfail bit signaturecritical area analysisintegrated circuit layout
 Summary | Full Text:PDF

Development of an Enterprise-Wide Yield Management System Using Critical Area Analysis for High-Product-Mix Semiconductor Manufacturing
Yuichi HAMAMURA Chizu MATSUMOTO Yoshiyuki TSUNODA Koji KAMODA Yoshio IWATA Kenji KANAMITSU Daisuke FUJIKI Fujihiko KOJIKA Hiromi FUJITA Yasuo NAKAGAWA Shun'ichi KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/01/01
Vol. E92-C  No. 1  pp. 144-152
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
defectsfailure analysisyield estimationintegrated circuit layoutsimulation
 Summary | Full Text:PDF