IEICE Trans

Chiou-Yng LEE

Scalable and Systolic Montgomery Multipliers over GF(2^m) Chin-Chin CHEN Chiou-Yng LEE Erl-Huei LU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/07/01 Vol. E91-A No. 7 pp. 1763-1771 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: systolic multiplier, Toeplitz matrix-vector, scalable architecture, Montgomery,
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Low-Complexity Parallel Systolic Montgomery Multipliers over GF(2^m) Using Toeplitz Matrix-Vector Representation Chiou-Yng LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/06/01 Vol. E91-A No. 6 pp. 1470-1477 Type of Manuscript: PAPER Category: Circuit Theory Keyword: bit-parallel systolic multiplier, Toeplitz matrix-vector, elliptic curve digital signature algorithm, trinomial, pentanomial,
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Concurrent Error Detection in Montgomery Multiplication over GF(2^m) Che-Wun CHIOU Chiou-Yng LEE An-Wen DENG Jim-Min LIN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/02/01 Vol. E89-A No. 2 pp. 566-574 Type of Manuscript: PAPER Category: Information Security Keyword: cryptography, Montgomery multiplication, finite field arithmetic, fault-tolerant computing, concurrent error detection,
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Efficient Design of Low-Complexity Bit-Parallel Systolic Hankel Multipliers to Implement Multiplication in Normal and Dual Bases of GF (2^m) Chiou-Yng LEE Che-Wun CHIOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/11/01 Vol. E88-A No. 11 pp. 3169-3179 Type of Manuscript: PAPER Category: Circuit Theory Keyword: finite fields, bit-parallel systolic multiplier, Hankel matrix, dual basis, normal basis,
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Low-Latency Bit-Parallel Systolic Multiplier for Irreducible x^m + xⁿ + 1 with GCD(m,n) = 1 Chiou-Yng LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/11/01 Vol. E86-A No. 11 pp. 2844-2852 Type of Manuscript: PAPER Category: Algorithms and Data Structures Keyword: bit-parallel systolic multiplier, finite field, irreducible trinomial,
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Computation of AB² Multiplier in GF(2^m) Using an Efficient Low-Complexity Cellular Architecture Chung-Hsin LIU Nen-Fu HUANG Chiou-Yng LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2657-2663 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: inner product, cyclic shifting, bit-parallel cellular array multipliers, irreducible AOP, canonical basis,
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