Chin-Ngai SZE


Navigating Register Placement for Low Power Clock Network Design
Yongqiang LU Chin-Ngai SZE Xianlong HONG Qiang ZHOU Yici CAI Liang HUANG Jiang HU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3405-3411
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Floorplan and Placement
Keyword: 
clock networkstandard cellquadratic placementprescribed skew
 Summary | Full Text:PDF

Accelerating Logic Rewiring Using Implication Analysis Tree
Chin-Ngai SZE Wangning LONG Yu-Liang WU Jinian BIAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2725-2736
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
alternative wirelogic transformationlogic synthesis
 Summary | Full Text:PDF