IEICE Trans

Chien-Ming WU

Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders Ming-Der SHIEH Tai-Ping WANG Chien-Ming WU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/09/01 Vol. E91-D No. 9 pp. 2300-2311 Type of Manuscript: PAPER Category: VLSI Systems Keyword: Viterbi decoder (VD), in-place scheduling, path metric memory management, VLSI architecture,
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High-Speed Design of Montgomery Inverse Algorithm over GF(2^m) Ming-Der SHIEH Jun-Hong CHEN Chien-Ming WU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/02/01 Vol. E89-A No. 2 pp. 559-565 Type of Manuscript: PAPER Category: Information Security Keyword: finite field, modular inverse arithmetic, Montgomery algorithm, cryptography,
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Exploring General Memory Structures in Turbo Decoders Using Sliding-Window MAP Algorithm Chien-Ming WU Ming-Der SHIEH Chien-Hsing WU
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2003/11/01 Vol. E86-B No. 11 pp. 3163-3173 Type of Manuscript: PAPER Category: Communication Devices/Circuits Keyword: turbo code, BCJR algorithm, MAP algorithm, sliding window algorithm, memory management,
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Novel Algorithms and VLSI Design for Division over GF(2^m) Chien-Hsing WU Chien-Ming WU Ming-Der SHIEH Yin-Tsung HWANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/05/01 Vol. E85-A No. 5 pp. 1129-1139 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: division algorithm, basis matrix, Stein's algorithm, high speed, finite field,
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