Chia-Chun TSAI


Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement
Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A  No. 2  pp. 706-716
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock routingdesign for manufacturabilitydouble viaX-architecture
 Summary | Full Text:PDF

GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay
Chia-Chun TSAI Jan-Ou WU Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A  No. 1  pp. 365-374
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoCclock treezero skewgrey relational clusteringDME (deferred-merge embedding)RLC delay model
 Summary | Full Text:PDF

Zero-Skew Driven Buffered RLC Clock Tree Construction
Jan-Ou WU Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/03/01
Vol. E90-A  No. 3  pp. 651-658
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock treeupward propagationbuffer insertionzero skewSoC
 Summary | Full Text:PDF

A New Approach to the Ball Grid Array Package Routing
Shuenn-Shi CHEN Jong-Jang CHEN Trong-Yen LEE Chia-Chun TSAI Sao-Jie CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2599-2608
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
ball grid array (BGA)pin grid array (PGA)inversion table
 Summary | Full Text:PDF