Chang-Kyung SEONG


A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator
Chang-Kyung SEONG Seung-Woo LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/05/01
Vol. E91-B  No. 5  pp. 1397-1402
Type of Manuscript:  PAPER
Category: Devices/Circuits for Communications
Keyword: 
burst-modeclock and data recovery circuitdigital phase alignerphase interpolator
 Summary | Full Text:PDF

A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution
Chang-Kyung SEONG Seung-Woo LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/01/01
Vol. E90-C  No. 1  pp. 165-170
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
dual-loop clock and data recovery (CDR)phase interpolatorphase resolution
 Summary | Full Text:PDF