Bo YANG


Experimental Study on a 5.8 GHz Power-Variable Phase-Controlled Magnetron
Bo YANG Tomohiko MITANI Naoki SHINOHARA 
Publication:   
Publication Date: 2017/10/01
Vol. E100-C  No. 10  pp. 901-907
Type of Manuscript:  Special Section PAPER (Special Section on Microwave and Millimeter-Wave Technology)
Category: 
Keyword: 
5.8 GHz magnetronphase locked loopwireless power transferphased array
 Summary | Full Text:PDF(2MB)

Low-Cost Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip
Ruilian XIE Jueping CAI Xin XIN Bo YANG 
Publication:   
Publication Date: 2017/04/01
Vol. E100-D  No. 4  pp. 910-913
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
Network-on-Chip (NoC)fault toleranceadaptive routingturn model
 Summary | Full Text:PDF(233.4KB)

Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming
Yu ZHANG Gong CHEN Bo YANG Jing LI Qing DONG Ming-Yu LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2487-2498
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
circuit synthesisSTIWPEchannel length modulationgeometric programming
 Summary | Full Text:PDF(5.4MB)

Structured Analog Circuit and Layout Design with Transistor Array
Bo YANG Qing DONG Jing LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2475-2486
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
transistor arraychannel decompositionstructured analog designmanufacturability
 Summary | Full Text:PDF(2.5MB)

Traffic Flow Simulator Using Virtual Controller Model
Haijun LIANG Hongyu YANG Bo YANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/01/01
Vol. E96-A  No. 1  pp. 391-393
Type of Manuscript:  LETTER
Category: Intelligent Transport System
Keyword: 
air traffic controltraffic flow managementvirtual controller modesimulation
 Summary | Full Text:PDF(368.2KB)

Layout-Aware Variability Characterization of CMOS Current Sources
Bo LIU Bo YANG Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 696-705
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
process variationcurrent mismatchlayout-dependent variationanalog DFM
 Summary | Full Text:PDF(1.9MB)

Cryptanalysis of Strong Designated Verifier Signature Scheme with Non-delegatability and Non-transferability
Mingwu ZHANG Tsuyoshi TAKAGI Bo YANG Fagen LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/01/01
Vol. E95-A  No. 1  pp. 259-262
Type of Manuscript:  Special Section LETTER (Special Section on Cryptography and Information Security)
Category: 
Keyword: 
strong designated verifier signatureunforgeabilitynon-delegatabilitynon-transferabilityprivacy of signer identity
 Summary | Full Text:PDF(86.2KB)

Software Reliability Modeling Considering Fault Correction Process
Lixin JIA Bo YANG Suchang GUO Dong Ho PARK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1  pp. 185-188
Type of Manuscript:  LETTER
Category: Software Engineering
Keyword: 
software reliabilitysoftware testingfault correction processcontinuous-time Markov chainmaximum likelihood estimation
 Summary | Full Text:PDF(190.2KB)

Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming
Qing DONG Bo YANG Jing LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3103-3110
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
placementfloorplanbuffer insertionmodule resizinggeometric programming
 Summary | Full Text:PDF(337.1KB)

Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver
Bo YANG Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3052-3060
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
power-MOSFETmetalization patternshape optimization
 Summary | Full Text:PDF(366.7KB)

A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion
Bo YANG Hiroshi MURATA Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2  pp. 542-549
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
DMOSfinite element methoddomain decompositionsub-domain reuseresistance extraction
 Summary | Full Text:PDF(443.2KB)