Atsushi WADA

A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm
Hao SAN Yoshitaka JINGU Hiroki WADA Hiroyuki HAGIWARA Akira HAYAKAWA Haruo KOBAYASHI Tatsuji MATSUURA Kouichi YAHAGI Junya KUDOH Hideo NAKANE Masao HOTTA Toshiro TSUKADA Koichiro MASHIKO Atsushi WADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/06/01
Vol. E90-C  No. 6  pp. 1181-1188
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
complex bandpass ΔΣAD modulator, I, Q path mismatches, dynamic matching, miltibit, data-weighted averaging, 
 Summary | Full Text:PDF
Complex Bandpass ΔΣAD Modulator Architecture without I, Q-Path Crossing Layout
Hao SAN Akira HAYAKAWA Yoshitaka JINGU Hiroki WADA Hiroyuki HAGIWARA Kazuyuki KOBAYASHI Haruo KOBAYASHI Tatsuji MATSUURA Kouichi YAHAGI Junya KUDOH Hideo NAKANE Masao HOTTA Toshiro TSUKADA Koichiro MASHIKO Atsushi WADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 908-915
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
complex bandpass ΔΣAD modulator, I, Q path mismatches, dynamic matching, multiplexer, 
 Summary | Full Text:PDF
High-Speed Continuous-Time Subsampling Bandpass ΔΣ AD Modulator Architecture Employing Radio Frequency DAC
Masafumi UEMORI Haruo KOBAYASHI Tomonari ICHIKAWA Atsushi WADA Koichiro MASHIKO Toshiro TSUKADA Masao HOTTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 916-923
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
continuous-time, subsampling, bandpass, ΔΣ modulator, RF DAC, jitter, 
 Summary | Full Text:PDF
Top-Down Design Methodology of Mixed Signal with Analog-HDL
Atsushi WADA Kuniyuki TANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 441-446
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
video-speed ADC, pipeline-type ADC, top-down design methodology, 
 Summary | Full Text:PDF