IEICE Trans

Atsushi TAKAHASHI

Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism Yuta UKON Shimpei SATO Atsushi TAKAHASHI
Publication: Publication Date: 2021/07/01 Vol. E104-C No. 7 pp. 309-318 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: digital circuit design, variable-latency circuit, signal monitoring, approximate completion-detection mechanism,
	Summary \| Full Text:PDF(2MB)

A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections Shimpei SATO Kano AKAGI Atsushi TAKAHASHI
Publication: Publication Date: 2020/09/01 Vol. E103-A No. 9 pp. 1037-1044 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: routing algorithm, set-pair routing problem, PCB, interposer,
	Summary \| Full Text:PDF(1015.2KB)

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution Shimpei SATO Eijiro SASSA Yuta UKON Atsushi TAKAHASHI
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 pp. 1760-1769 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: circuit design, variable-latency circuit, speculative execution, general-synchronous circuit, timing-error detection,
	Summary \| Full Text:PDF(1.5MB)

A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning Takeshi IHARA Toshiyuki HONGO Atsushi TAKAHASHI Chikaaki KODAMA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1473-1480 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: self-aligned quadruple patterning (SAQP), routing algorithm, turn prohibition constraint,
	Summary \| Full Text:PDF(1.8MB)

A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model Ahmed AWAD Atsushi TAKAHASHI Chikaaki KODAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2363-2374 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: pattern fidelity, process variation, mask manufacturability, mask data volume, computation time,
	Summary \| Full Text:PDF(1.7MB)

A Length Matching Routing Algorithm for Set-Pair Routing Problem Yuta NAKATANI Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2565-2571 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: set-pair routing, interposer, PCB, routing algorithm,
	Summary \| Full Text:PDF(908.5KB)

A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization Yiqiang SHENG Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2418-2426 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: NP-hard problem, optimization, conflicting objectives, physical design, placement,
	Summary \| Full Text:PDF(2.2MB)

2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework Yukihide KOHIRA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2459-2466 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: general-synchronous framework, multi-domain clock skew scheduling, two-domain clock skew scheduling, 2-SAT,
	Summary \| Full Text:PDF(430.7KB)

Flow Control Scheme Using Adaptive Receiving Opportunity Control for Wireless Multi-Hop Networks Atsushi TAKAHASHI Nobuyoshi KOMURO Shiro SAKATA Shigeo SHIODA Tutomu MURASE
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2012/09/01 Vol. E95-B No. 9 pp. 2751-2758 Type of Manuscript: Special Section PAPER (Special Section on Emerging Technologies and Applications for Ad Hoc and Wireless Mesh Networks) Category: Keyword: quality of service, wireless LAN, admission control, multi-hop networks,
	Summary \| Full Text:PDF(1.5MB)

FOREWORD Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2481-2481 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF(113.6KB)

Single-Layer Trunk Routing Using Minimal 45-Degree Lines Kyosuke SHINODA Yukihide KOHIRA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2510-2518 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: printed circuit board, planar routing, trunk routing, routing density, 45-degree line,
	Summary \| Full Text:PDF(1.4MB)

CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Yukihide KOHIRA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2380-2388 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: PCB routing, length-matching routing, trunk routing,
	Summary \| Full Text:PDF(1.9MB)

A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound Yukihide KOHIRA Suguru SUEHIRO Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 2971-2978 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Desing Keyword: routing design of PCB, longer path algorithm, upper bound of wire length,
	Summary \| Full Text:PDF(751.5KB)

MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages Yoichi TOMIOKA Yoshiaki KURATA Yukihide KOHIRA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 2998-3006 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Desing Keyword: ball grid array, monotonic, nearest via assignment, package routing, radiate,
	Summary \| Full Text:PDF(480.7KB)

Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages Yoichi TOMIOKA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/06/01 Vol. E92-A No. 6 pp. 1433-1441 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: ball grid array, monotonic, package routing, via assignment,
	Summary \| Full Text:PDF(550.9KB)

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework Yukihide KOHIRA Shuhei TANI Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1106-1114 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: delay insertion, clock scheduling, general-synchronous framework,
	Summary \| Full Text:PDF(835.2KB)

A Fast Clock Scheduling for Peak Power Reduction in LSI Yosuke TAKAHASHI Yukihide KOHIRA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3803-3811 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: clock scheduling, general-synchronous framework, peak power reduction, peak power wave estimation,
	Summary \| Full Text:PDF(825.6KB)

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3539-3547 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: FPGA prototyping, ILP, I/O pins constraint, verification, time-multiplexed I/O,
	Summary \| Full Text:PDF(309.4KB)

A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework Yukihide KOHIRA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/10/01 Vol. E91-A No. 10 pp. 3030-3037 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: register relocation, retiming, clock scheduling, general-synchronous framework,
	Summary \| Full Text:PDF(440.8KB)

Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements Bakhtiar Affendi ROSDI Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2736-2742 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: pipelined circuits, multi-clock cycle paths, clock scheduling, delay balancing,
	Summary \| Full Text:PDF(250.2KB)

Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization Yukihide KOHIRA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 800-807 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: register relocation, retiming, clock period minimization, generalized synchronous framework,
	Summary \| Full Text:PDF(357KB)

Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits Bakhtiar Affendi ROSDI Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3435-3442 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: pipelined circuits, multi-clock cycle paths, clock scheduling,
	Summary \| Full Text:PDF(409KB)

Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages Yoichi TOMIOKA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3551-3559 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: ball grid array, monotonic, single-layer, package, routing,
	Summary \| Full Text:PDF(865.5KB)

Practical Fast Clock-Schedule Design Algorithms Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 1005-1011 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: clock-schedule, shortest path, negative cycle detection, semi-synchronous circuits,
	Summary \| Full Text:PDF(159KB)

A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages Yukiko KUBO Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/05/01 Vol. E88-A No. 5 pp. 1283-1289 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: ball grid array, monotonic routing, via assignment, wire congestion, total wire length, heuristic,
	Summary \| Full Text:PDF(819.9KB)

Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion Yukihide KOHIRA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 892-898 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: delay insertion, clock period minimization, semi-synchronous circuit, delay-slack, delay-demand,
	Summary \| Full Text:PDF(277.9KB)

A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees Makoto SAITOH Masaaki AZUMA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2756-2763 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Clock Scheduling Keyword: semi-synchronous circuit, clustering, clock-scheduling, clock tree,
	Summary \| Full Text:PDF(968.4KB)

A Semi-Synchronous Circuit Design Method by Clock Tree Modification Seiichiro ISHIJIMA Tetsuaki UTSUMI Tomohiro OTO Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2596-2602 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Keyword: semi-synchronous circuit, clock tree, MIPS processor,
	Summary \| Full Text:PDF(978.4KB)

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling Keiichi KUROKAWA Takuya YASUI Yoichi MATSUMURA Masahiko TOYONAGA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2746-2755 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Clock Scheduling Keyword: clock scheduling, clock tree synthesis, high-speed, low power,
	Summary \| Full Text:PDF(1.4MB)

An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm Kengo R. AZEGAMI Masato INAGI Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/03/01 Vol. E85-A No. 3 pp. 655-663 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: circuit partition, hyper-graph partition, network flow, min-cut, integrated circuit design,
	Summary \| Full Text:PDF(614.2KB)

A Practical Clock Tree Synthesis for Semi-Synchronous Circuits Keiichi KUROKAWA Takuya YASUI Masahiko TOYONAGA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2705-2713 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Layout Keyword: semi-synchronous circuit, clock scheduling, environmental and manufacturing conditions, zero skew clock tree, various timing clock tree,
	Summary \| Full Text:PDF(1007KB)

An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut Kengo R. AZEGAMI Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/05/01 Vol. E84-A No. 5 pp. 1301-1308 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: circuit partition, hyper-graph partition, network flow, min-cut, integrated circuit design,
	Summary \| Full Text:PDF(506.1KB)

Clock Schedule Design for Minimum Realization Cost Tomoyuki YODA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2552-2557 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Performance Optimization Keyword: semi-synchronous circuit, clock schedule, clock tree,
	Summary \| Full Text:PDF(305KB)

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion Tomoyuki YODA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2383-2389 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: delay insertion, clock period minimization, semi-synchronous circuit,
	Summary \| Full Text:PDF(780.6KB)

Schedule-Clock-Tree Routing for Semi-Synchronous Circuits Kazunori INOUE Wataru TAKAHASHI Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2431-2439 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: clock-tree, clock-scheduling, semi-synchronous circuit, deferred-merge embedding,
	Summary \| Full Text:PDF(794.3KB)

Assignment of Intervals to Parallel Tracks with Minimum Total Cross-Talk Yasuhiro TAKASHIMA Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/09/25 Vol. E81-A No. 9 pp. 1909-1915 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: minimum cross-talk, assignment, intersecting interval sets,
	Summary \| Full Text:PDF(548.1KB)

Routability of FPGAs with Extremal Switch-Block Structures Yasuhiro TAKASHIMA Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/25 Vol. E81-A No. 5 pp. 850-856 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: FPGA, switch-block, routability, detailed-routing,
	Summary \| Full Text:PDF(583KB)

Computational Complexity Analysis of Set-Bin-Packing Problem Tomonori IZUMI Toshihiko YOKOMARU Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/25 Vol. E81-A No. 5 pp. 842-849 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: bin-packing, complexity, technology mapping, FPGA,
	Summary \| Full Text:PDF(682.7KB)

Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan Tomonori IZUMI Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/25 Vol. E81-A No. 5 pp. 857-865 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: floorplan, layout, area optimization, air-pressure, zero-wasted-area,
	Summary \| Full Text:PDF(757.9KB)

Cost-Radius Balanced Spanning/Steiner Trees Hideki MITSUBAYASHI Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/04/25 Vol. E80-A No. 4 pp. 689-694 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: delay, spanning tree, steiner tree, VLSI layout,
	Summary \| Full Text:PDF(418.3KB)

Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two Atsushi TAKAHASHI Shuichi UENO Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 pp. 1828-1839 Type of Manuscript: PAPER Category: Graphs and Networks Keyword: proper-path-width, path-width, minor-closed family, minimal forbidden minor, VLSI layout,
	Summary \| Full Text:PDF(1.1MB)

Universal Graphs for Graphs with Bounded Path-Width Atsushi TAKAHASHI Shuichi UENO Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/04/25 Vol. E78-A No. 4 pp. 458-462 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: universal graph, path-width, k-path, parallel computing,
	Summary \| Full Text:PDF(462.6KB)

On the Proper-Path-Decomposition of Trees Atsushi TAKAHASHI Shuichi UENO Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/01/25 Vol. E78-A No. 1 pp. 131-136 Type of Manuscript: LETTER Category: Graphs, Networks and Matroids Keyword: proper-path-width, proper-path-decomposition, path-width, path-decomposition, polynomial time algorithm,
	Summary \| Full Text:PDF(432.9KB)

A Switch-Box Router BOX-PEELER" and Its Tractable Problems Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1989/12/25 Vol. E72-E No. 12 pp. 1367-1373 Type of Manuscript: Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems) Category: VLSI Design Technology Keyword:
	Summary \| Full Text:PDF(574.7KB)