IEICE Trans

Atsushi IWATA

A New Multi-Path Routing Methodology Based on Logit-Type Probability Assignment Yudai HONMA Masaki AIDA Hideyuki SHIMONISHI Atsushi IWATA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2011/08/01 Vol. E94-B No. 8 pp. 2282-2291 Type of Manuscript: PAPER Category: Internet Keyword: multi-path routing, multinomial logit model, link-state protocol, distance-vector protocol,
	Summary \| Full Text:PDF

Background Calibration Techniques for Low-Power and High-Speed Data Conversion Atsushi IWATA Yoshitaka MURASAKA Tomoaki MAEDA Takafumi OHMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 923-929 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: digital assist analog circuit, flash ADC, comparator, current summing DAC, substrate noise,
	Summary \| Full Text:PDF

A Neural Recording Amplifier with Low-Frequency Noise Suppression Takeshi YOSHIDA Yoshihiro MASUI Ryoji EKI Atsushi IWATA Masayuki YOSHIDA Kazumasa UEMATSU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 pp. 849-854 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: neural recording amplifier, neural signal sensing LSI, 1/f noise, autozero technology,
	Summary \| Full Text:PDF

A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion Yoshihiro MASUI Takeshi YOSHIDA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/06/01 Vol. E92-C No. 6 pp. 828-834 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: scaled CMOS technology, voltage mismatch, DeltAMP, analog-time-digital conversion (ATD),
	Summary \| Full Text:PDF

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification Daisuke KOSAKA Makoto NAGATA Yoshitaka MURASAKA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2651-2660 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: chip-level substrate coupling, F-matrix computation, slice-and-stack substrate modeling,
	Summary \| Full Text:PDF

Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices Atsushi IWATA Takeshi YOSHIDA Mamoru SASAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1149-1155 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: low-noise amplifier, autozeroing, chopper stabilization, switched op-amp, VCO, ring oscillator,
	Summary \| Full Text:PDF

Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits Daisuke KOSAKA Makoto NAGATA Yoshitaka MURASAKA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/02/01 Vol. E90-A No. 2 pp. 380-387 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: substrate coupling, equivalent circuit modeling, guard ring, guard band, deep n-well, substrate noise analysis, S21 measurement, F-matrix computation,
	Summary \| Full Text:PDF

A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory Kan'ya SASAKI Takashi MORIE Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1637-1644 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: spiking neuron model, feedback network, global excitatory unit, negative thresholding, associative memory,
	Summary \| Full Text:PDF

An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture Osamu NOMURA Takashi MORIE Keisuke KOREKADO Teppei NAKANO Masakazu MATSUGU Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/06/01 Vol. E89-C No. 6 pp. 781-791 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Keyword: object detection/recognition, convolutional neural network, image-filtering, multiply-and-accumulation operation, LSI architecture,
	Summary \| Full Text:PDF

A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique Takeshi YOSHIDA Yoshihiro MASUI Takayuki MASHIMO Mamoru SASAKI Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/06/01 Vol. E89-C No. 6 pp. 769-774 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Keyword: low-noise amplifier, autozeroing, chopper stabilization, low-voltage operation, switched op-amp, CMOS,
	Summary \| Full Text:PDF

Improving Ethernet Reliability and Stability Using Global Open Ethernet Technology Masaki UMAYABASHI Youichi HIDAKA Nobuyuki ENOMOTO Daisaku OGASAHARA Kazuo TAKAGI Atsushi IWATA Akira ARUTAKI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2006/03/01 Vol. E89-B No. 3 pp. 675-682 Type of Manuscript: Special Section PAPER (Special Section on the Next Generation Ethernet Technologies) Category: Keyword: Ethernet, virtual private network, rapid spanning tree protocol, VLAN tag, failure recovery,
	Summary \| Full Text:PDF

Carrier-Grade Ethernet Technologies for Next Generation Wide Area Ethernet Atsushi IWATA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2006/03/01 Vol. E89-B No. 3 pp. 651-660 Type of Manuscript: INVITED PAPER (Special Section on the Next Generation Ethernet Technologies) Category: Keyword: MAN, Ethernet, reliability, QoS, OAM,
	Summary \| Full Text:PDF

A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique Mitsuru SHIOZAKI Toru MUKAI Masahiro ONO Mamoru SASAKI Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/06/01 Vol. E88-C No. 6 pp. 1233-1240 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Optical, PLL Keyword: CDMA, robot, multiplex, synchronization technique,
	Summary \| Full Text:PDF

Pulse Modulation Techniques for Nonlinear Dynamical Systems and a CMOS Chaos Circuit with Arbitrary 1-D Maps Takashi MORIE Kenichi MURAKOSHI Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1856-1862 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: CMOS analog integrated circuits, nonlinear circuits, nonlinear functions, pulse width modulation, pulse phase modulation, chaos,
	Summary \| Full Text:PDF

Design of a Wireless Neural-Sensing LSI Takeshi YOSHIDA Miho AKAGI Takayuki MASHIMO Atsushi IWATA Masayuki YOSHIDA Kazumasa UEMATSU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/06/01 Vol. E87-C No. 6 pp. 996-1002 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Keyword: neural-sensing LSI, wireless communication, multi-input-channels, chopper amplifier, flicker noise, multi-mode ADC,
	Summary \| Full Text:PDF

A Design of Neural Signal Sensing LSI with Multi-Input-Channels Takeshi YOSHIDA Takayuki MASHIMO Miho AKAGI Atsushi IWATA Masayuki YOSHIDA Kazumasa UEMATSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/02/01 Vol. E87-A No. 2 pp. 376-383 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: neural signal sensing LSI, multi-input-channels probe, flicker noise, chopper amplifier, multi-mode ADC,
	Summary \| Full Text:PDF

Global Open Ethernet Architecture for a Cost-Effective Scalable VPN Solution Atsushi IWATA Youichi HIDAKA Masaki UMAYABASHI Nobuyuki ENOMOTO Akira ARUTAKI Kazuo TAKAGI Dirceu CAVENDISH Rauf IZMAILOV
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2004/01/01 Vol. E87-B No. 1 pp. 142-151 Type of Manuscript: PAPER Category: Internet Keyword: Ethernet, global, VPN, VLAN, scalable,
	Summary \| Full Text:PDF

A Pulse-Coupled Neural Network Simulator Using a Programmable Gate Array Technique Kousuke KATAYAMA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-D No. 5 pp. 872-881 Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing) Category: Keyword: pulse-coupled neural network, phase-locked loops, dendritic tree, programmable gate array, reconfigurable network,
	Summary \| Full Text:PDF

A High-Resolution CMOS Image Sensor with Hadamard Transform Function Kousuke KATAYAMA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/02/01 Vol. E86-A No. 2 pp. 396-403 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: orthogonal transform, Hadamard transform, functional image sensor,
	Summary \| Full Text:PDF

An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing Kousuke KATAYAMA Atsushi IWATA Takashi MORIE Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/08/01 Vol. E85-C No. 8 pp. 1596-1603 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance Analog Integrated Circuits) Category: Keyword: Hadamard transform, image sensor, pulse width modulation technique, charge sharing,
	Summary \| Full Text:PDF

FOREWORD Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/08/01 Vol. E85-C No. 8 pp. 1527-1528 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF

Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques Hiroshi ANDO Takashi MORIE Makoto MIYAKE Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/02/01 Vol. E85-A No. 2 pp. 381-388 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: resistive-fuse network, oscillator network, image segmentation, image extraction, pulse modulation circuit,
	Summary \| Full Text:PDF

A CMOS Stochastic Associative Processor Using PWM Chaotic Signals Toshio YAMANAKA Takashi MORIE Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/12/01 Vol. E84-C No. 12 pp. 1723-1729 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Systems with New Concepts) Category: Keyword: pulse-width modulation, PWM, chaotic signals, stochastic association,
	Summary \| Full Text:PDF

Merged Analog-Digital Circuits Using Pulse Modulation for Intelligent SoC Applications Atsushi IWATA Takashi MORIE Makoto NAGATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/02/01 Vol. E84-A No. 2 pp. 486-496 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit Techniques Supporting the System LSI Era) Category: Keyword: pulse modulation, mixed analog-digital integrated circuits, nonlinear dynamical systems, switched current integration, time-domain signal processing,
	Summary \| Full Text:PDF

A Nonlinear Oscillator Network for Gray-Level Image Segmentation and PWM/PPM Circuits for Its VLSI Implementation Hiroshi ANDO Takashi MORIE Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/02/25 Vol. E83-A No. 2 pp. 329-336 Type of Manuscript: Special Section PAPER (Special Section on Intelligent Signal and Image Processing) Category: Keyword: nonlinear oscillator network, LEGION, image segmentation, pulse modulation, PWM, PPM, LSI implementation,
	Summary \| Full Text:PDF

New Non-Volatile Analog Memory Circuits Using PWM Methods Shigeo KINOSHITA Takashi MORIE Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1655-1661 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Non-Binary Architectures Keyword: analog memory, floating gate device, pulse width modulation, PWM,
	Summary \| Full Text:PDF

Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 271-278 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog-digital mixed LSI, substrate noise, crosstalk, AnalogHDL, behavioral modeling, macroscopic substrate noise model, ΔΣADC,
	Summary \| Full Text:PDF

An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique Takashi MORIE Jun FUNAKOSHI Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 356-363 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: LSI implementation, neural network, pulse width modulation, PWM,
	Summary \| Full Text:PDF

A Stochastic Associative Memory Using Single-Electron Tunneling Devices Makoto SAEN Takashi MORIE Makoto NAGATA Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/01/25 Vol. E81-C No. 1 pp. 30-35 Type of Manuscript: Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices) Category: Keyword: associative memory, single-electron tunneling, SET, single-electron transistor,
	Summary \| Full Text:PDF

Analysis and Design of Low Loss and Low Mode-Shift Integrated Optical Waveguides Using Finite-Difference Time-Domain Method Takeshi DOI Atsushi IWATA Masataka HIROSE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/05/25 Vol. E80-C No. 5 pp. 625-631 Type of Manuscript: Special Section PAPER (Special Issue on Photonic Integrated Circuits) Category: Keyword: integrated optical waveguide, finite-difference time-domain method, double-reflection waveguide, slit branch waveguide,
	Summary \| Full Text:PDF

FOREWORD Atsushi IWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/02/25 Vol. E80-A No. 2 pp. 261-262 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF

ATM Routing Algorithms with Multiple QOS Requirements for Multimedia Internetworking Atsushi IWATA Rauf IZMAILOV Duan-Shin LEE Bhaskar SENGUPTA G. RAMAMURTHY Hiroshi SUZUKI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1996/08/25 Vol. E79-B No. 8 pp. 999-1007 Type of Manuscript: INVITED PAPER (Special Issue on Multimedia on Demand) Category: Keyword: path selection algorithm, QOS, routing signaling, traffic class, ATM, PNNI, multimedia,
	Summary \| Full Text:PDF

FOREWORD Atsushi IWATA Ian YOUNG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/25 Vol. E79-C No. 7 pp. 881-882 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF

A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's Atsushi IWATA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/02/25 Vol. E79-A No. 2 pp. 145-157 Type of Manuscript: Special Section PAPER (Special Section on Analog Technologies in Submicron Era) Category: Keyword: pulse width modulation (PWM), switched current integrator, PWM adder, PWM signal converter,
	Summary \| Full Text:PDF

FOREWORD Kevin J. O'CONNOR Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/06/25 Vol. E78-C No. 6 pp. 587-588 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF

FOREWORD Atsushi IWATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 pp. 1027-1028 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF

Optical Interconnections as a New LSI Technology Atsushi IWATA Izuo HAYASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/01/25 Vol. E76-C No. 1 pp. 90-99 Type of Manuscript: INVITED PAPER (Special Issue on Opto-Electronics and LSI) Category: Integration of Opto-Electronics and LSI Technologies Keyword: optical interconnection, CMOS micro processor, laser diodes, photo ditectors, optical wave guides, multichip module, clock circuit, bus line,
	Summary \| Full Text:PDF

Real-Time Feed-Forward Control LSIs for a Direct Wafer Exposure Electron Beam System Hironori YAMAUCHI Tetsuo MOROSAWA Takashi WATANABE Atsushi IWATA Tsutomu HOSAKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/01/25 Vol. E76-C No. 1 pp. 124-135 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: asic, pipeline, adaptive, electron beam,
	Summary \| Full Text:PDF

Present and Future Trends in Integrated Analog Signal Processing Circuits Kenji NAKAYAMA Atsushi IWATA Takeshi YANAGISAWA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1988/12/25 Vol. E71-E No. 12 pp. 1177-1188 Type of Manuscript: REVIEW PAPER Category: Keyword:
	Summary \| Full Text:PDF