Atsushi HIRAISHI

Application of Circuit-Level Hot-Carrier Reliability Simulation to Memory Design
Peter M. LEE Tsuyoshi SEO Kiyoshi ISE Atsushi HIRAISHI Osamu NAGASHIMA Shoji YOSHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/04/25
Vol. E81-C  No. 4  pp. 595-601
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
hot-carrier degradation, reliability, device lifetime, circuit simulation, SRAM, DRAM, 
 Summary | Full Text:PDF
A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM
Hideharu YAHATA Yoji NISHIO Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Atsushi HIRAISHI Yoshitaka KINOSHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 557-565
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
CMOS, high speed, cache SRAM, chip floor plan, sense amplifier, output register, setup/hold time, 
 Summary | Full Text:PDF