Aravind THARAYIL NARAYANAN


A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock
Haosheng ZHANG Aravind THARAYIL NARAYANAN Hans HERDIAN Bangan LIU Rui WU Atsushi SHIRANE Kenichi OKADA 
Publication:   
Publication Date: 2019/04/01
Vol. E102-C  No. 4  pp. 276-286
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
VCOchip-scale atomic clock (CSAC)power efficiencyphase noisetank loadingtail filter
 Summary | Full Text:PDF

A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI
Aravind THARAYIL NARAYANAN Wei DENG Dongsheng YANG Rui WU Kenichi OKADA Akira MATSUZAWA 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 259-267
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
fully-synthesizableall-digitalclock data recoveryinjection lockingphase-filtering
 Summary | Full Text:PDF

An AM-PM Noise Mitigation Technique in Class-C VCO
Kento KIMURA Aravind THARAYIL NARAYANAN Kenichi OKADA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/12/01
Vol. E98-C  No. 12  pp. 1161-1170
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
VCOClass-CAM-PM conversionparasitic capacitancecross coupled pairnoise sensitivity
 Summary | Full Text:PDF