IEICE Trans

Akira TSUCHIYA

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm² Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS Akira TSUCHIYA Akitaka HIRATSUKA Kenji TANAKA Hiroyuki FUKUYAMA Naoki MIURA Hideyuki NOSAKA Hidetoshi ONODERA
Publication: Publication Date: 2020/10/01 Vol. E103-C No. 10 pp. 489-496 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Integrated Electronics Keyword: optical communication, transimpedance amplifier, inductive peaking, on-chip inductor,
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Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity Akira TSUCHIYA Akitaka HIRATSUKA Toshiyuki INOUE Keiji KISHINE Hidetoshi ONODERA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 573-579 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: power integrity, signal integrity, multi-layered inductor,
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A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage Norihiro KAMAE Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/06/01 Vol. E98-C No. 6 pp. 504-511 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: body bias generator, dynamic voltage frequency scaling, low supply voltage, analog-assisted digital, switched-capacitor circuits,
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Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure SinNyoung KIM Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 pp. 325-331 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: radiation-hardened phase-locked loop (RH-PLL), PLL, radiation-hardened-by-design (RHBD), dual modular redundancy (DMR),
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Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop SinNyoung KIM Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/03/01 Vol. E97-A No. 3 pp. 768-776 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: radiation-hardened phase-locked loop (RH-PLL), soft error, clock-perturbation model,
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A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation Norihiro KAMAE Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/03/01 Vol. E97-A No. 3 pp. 734-740 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: body bias generator, dynamic voltage frequency scaling, analog-assisted digital, low supply voltage,
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Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System Takeshi KUBOKI Yusuke OHTOMO Akira TSUCHIYA Keiji KISHINE Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/02/01 Vol. E95-A No. 2 pp. 479-486 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: interwoven inductor, LD driver, optical communication,
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Statistical Gate Delay Model for Multiple Input Switching Takayuki FUKUOKA Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3070-3078 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: statistical static timing analysis, multiple input switching, statistical maximum operation,
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Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration Masanori HASHIMOTO Jangsombatsiri SIRIPORN Akira TSUCHIYA Haikun ZHU Chung-Kuan CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3474-3480 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: eye-diagram, on-chip transmission line, waveform distortion, resistive termination, shunt conductance,
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Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver Takeshi KUBOKI Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1274-1281 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: on-chip signaling, current-mode logic,
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Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1267-1273 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: on-chip transmission-line, termination,
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Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3585-3593 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: parameter extraction, transmission-line, frequency dependence,
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Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design Toshiki KANAMOTO Tatsuhiko IKEDA Akira TSUCHIYA Hidetoshi ONODERA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3560-3568 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: substrate, interconnect, resistance, inductance, SoC,
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Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect Yoichi YUYAMA Akira TSUCHIYA Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 327-333 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Interface and Interconnect Techniques Keyword: alternate self shielding, on-chip global interconnect, critical transition and bus encoding,
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Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 885-891 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: global interconnect, high-speed signaling, performance limitation,
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Representative Frequency for Interconnect R(f)L(f)C Extraction Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2942-2951 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: interconnect, extraction, frequency-dependent,
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