Akira MOTOHARA


A Practical Method for System-Level Bus Architecture Validation
Kazuyoshi TAKEMURA Masanobu MIZUNO Akira MOTOHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2439-2445
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Methodology
Keyword: 
system-level designbus architecture validationbus-cycle-accuratebehavioral modelinterface model
 Summary | Full Text:PDF(369KB)

A Partial Scan Design Approach based on Register-Transfer Level Testability Analysis
Akira MOTOHARA Sadami TAKEOKA Mitsuyasu OHTA Michiaki MURAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1436-1442
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Design for Testability
Keyword: 
design for testabilitypartial scan designregister-transfer levelautomatic test-pattern generationESDA
 Summary | Full Text:PDF(732.9KB)

Test Generation for Sequential Circits Using Partitioned Image Computation
Hoyong CHOI Hironori MAEDA Takashi KOHARA Nagisa ISHIURA Isao SHIRAKAWA Akira MOTOHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1770-1774
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
test generation for sequential circuittproduct machine traversal methodmixed breadth-first/depth-first traversalpartitioned image computation
 Summary | Full Text:PDF(350.1KB)

A Scheme for Mixed-Mode Fault Simulation
Akira MOTOHARA Motohide MURAKAMI Miki URANO Yasuo MASUDA Masahide SUGANO 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/12/25
Vol. E71-E  No. 12  pp. 1229-1235
Type of Manuscript:  Special Section PAPER (Special Issue on CAS Karuizawa Workshop)
Category: 
Keyword: 
 Summary | Full Text:PDF(576KB)

Fast Test Pattern Generation Using a Multiprocessor System
Hideo FUJIWARA Akira MOTOHARA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/04/25
Vol. E71-E  No. 4  pp. 441-447
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
 Summary | Full Text:PDF(503.1KB)