Akihisa YAMADA

FOREWORD
Akihisa YAMADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1355-1355
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(223.4KB)
FOREWORD
Akihisa YAMADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2366-2366
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(218.7KB)
Hardware Algorithm Optimization Using Bach C
Kazuhisa OKADA Akihisa YAMADA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4  pp. 835-841
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
high level synthesis, behavioral synthesis, C language, Bach C, 
 Summary | Full Text:PDF(341.7KB)
Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes
Mizuki TAKAHASHI Nagisa ISHIURA Akihisa YAMADA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2456-2463
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Co-design and High-level Synthesis
Keyword: 
behavioral partitioning, thread composition, behavioral synthesis, 
 Summary | Full Text:PDF(671.1KB)
Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
Masayuki YAMAGUCHI Akihisa YAMADA Toshihiro NAKAOKA Takashi KAMBE Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1853-1860
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
performance evaluation, datapath, structure, parallel constraint, 
 Summary | Full Text:PDF(751.3KB)
Datapath Scheduling for Behavioral Description with Conditional Branches
Akihisa YAMADA Toshiki YAMAZAKI Nagisa ISHIURA Isao SHIRAKAWA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 1999-2009
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesis, datapath scheduling, 0-1 integer programming problem, binary decision diagram, branch-and-bound method, 
 Summary | Full Text:PDF(902.6KB)
An Automatic Layout Generator for Bipolar Analog Modules
Takao ONOYE Akihisa YAMADA Itthichai ARUNGSRISANGCHAI Masakazu TANAKA Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1306-1314
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
layout generator, analog curcuit, one-dimensianal array, block compaction, 
 Summary | Full Text:PDF(708.3KB)