Akihiko HASHIGUCHI


Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor
Takahiro SEKI Satoshi AKUI Katsunori SENO Masakatsu NAKAI Tetsumasa MEGURO Tetsuo KONDO Akihiko HASHIGUCHI Hirokazu KAWAHARA Kazuo KUMANO Masayuki SHIMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 520-527
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
adaptive supply voltage controlautonomous clock frequency controlleakage power compensationembedded DRAMwideband bus architecture
 Summary | Full Text:PDF

5. 4 GOPS, 81 GB/s Linear Array Architecture DSP
Akihiko HASHIGUCHI Masuyoshi KUROKAWA Ken'ichiro NAKAMURA Hiroshi OKUDA Koji AOYAMA Mitsuharu OHKI Katsunori SENO Ichiro KUMATA Masatoshi AIKAWA Hirokazu HANAKI Takao YAMAZAKI Mitsuo SONEDA Seiichiro IWASE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 661-668
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
videoparallel processingSIMDDSP
 Summary | Full Text:PDF