A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Fara ASHIKIN  Masaki HASHIZUME  Hiroyuki YOTSUYANAGI  Shyue-Kung LU  Zvi ROTH  

Publication:   IEICE TRANSACTIONS on Information and Systems
Publicized: 2018/05/09
DOI: 10.1587/transinf.2018EDP7093
Full Text: PDF(2MB)