Three dimensional FPGA architecture with fewer TSVs

Motoki AMAGASAKI  Masato IKEBE  Qian ZHAO  Masahiro IIDA  Toshinori SUEYOSHI  

Publication:   IEICE TRANSACTIONS on Information and Systems
Publicized: 2017/11/17
DOI: 10.1587/transinf.2017RCP0008
Full Text: PDF(741KB)