Design exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V processor

Jinli RAO  Tianyong AO  Shu XU  Kui DAI  Xuecheng ZOU  

Publication:   IEICE TRANSACTIONS on Information and Systems
Publicized: 2018/08/22
DOI: 10.1587/transinf.2017ICP0019
Full Text: PDF(666KB)