A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line

Yoshinobu HIGAMI  Senling WANG  Hiroshi TAKAHASHI  Shin-ya KOBAYASHI  Kewal K. SALUJA  

Publication:   IEICE TRANSACTIONS on Information and Systems
Publicized: 2017/06/12
DOI: 10.1587/transinf.2016EDL8210
Full Text: PDF(64.6KB)