Development of a Power Efficient SMT Processor with Heterogeneous Instruction Set Architectures

Kazuhiro YOSHIMURA  Takashi NAKADA  Yasuhiko NAKASHIMA  Toshiaki KITAMURA 

Publication
D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition)  Vol.J95-D  No.6  pp.1334-1346
Publication Date: 2012/06/01
Online ISSN: 1881-0225
Print ISSN: 1880-4535
Type of Manuscript: PAPER
Category: 
Keyword: 
VLIW/superscalar mixed architecture,  multithreading,  LSI prototyping,  processor development environment, 

Full Text(in Japanese): PDF(1022.7KB)

Summary: 
The use of heterogeneous multi-core processors is very popular. However, multi-core processors that increase the chip area by directly incorporating discrete cores are not the best solution for power consumption. Therefore, we developed a heterogeneous SMT processor named OROCHI on a step-by-step development environment. OROCHI is capable of executing two threads simultaneously by resource sharing between VLIW and superscalar units. Based on an ASIC implementation, we compared OROCHI with a heterogeneous multi-core processor. The evaluation results show that the power efficiency of OROCHI is 1.31 times better, using only 79% of the chip area of the multi-core processor.