A Study on Practical Use of Power Noise Analysis Technique Using Random Walk Method

Hitoshi MIWA  Goro SUZUKI 

Publication
A - Abstracts of IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (Japanese Edition)  Vol.J95-A  No.6  pp.539-543
Publication Date: 2012/06/01
Online ISSN: 1881-0195
Print ISSN: 0913-5707
Type of Manuscript: LETTER
Category: 
Keyword: 
circuit analysis,  random walk,  KCL, 

Full Text(in Japanese): PDF(497.9KB)

Summary: 
Random walk method is one of the methods that solve differential equations for transient analysis of VLSI power network model which consist of resistors and capacitors. We propose techniques that realize 5[%] analysis error compared with the results of differential equation direct solver such as SPICE. In the conventional random walk method, the number of games is fixed when the voltage that is tentatively calculated after every game converges. The 5[%] analysis error had not been realized because the voltage convergence has no relation with the error. Since there are many factors that cause the error, it is difficult to theoretically evaluate the error and fix the number of games. In order to realize the 5[%] analysis error, we clarify what are the error factors. We propose to fix the number of games using lookup tables that store empirical values. The experimental result using 80-840 node circuit blocks in actual VLSI shows that the error is 2.1[%] when the lookup table is used. The total number of games for 22 node analysis is 2.9 times smaller than that when conventional method achieves 6.0[%] error.