Study of Pattern Area Reduction with 3 Dimensional Transistor for Logic Circuit

Yu HIROSHIMA  Takahiro KODAMA  Shigeyoshi WATANABE  

Publication
C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)   Vol.J94-C   No.10   pp.341-345
Publication Date: 2011/10/01
Online ISSN: 1881-0217
DOI: 
Print ISSN: 1345-2827
Type of Manuscript: LETTER
Category: 
Keyword: 
FinFET,  double gate transistor,  stacked type transistor,  full added,  pattern area,  

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Summary: 
Pattern area reduction with 3 dimensional transistor and various kind of circuit scheme for logic circuit such as full adder has been newly studied. Pattern area reduction ratio with 3 dimensional transistor is large for full adder consisted with large number of transistor. In the case for full adder consisted with small number of transistor, the pattern area reduction ratio is relatively small.