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Study of Pattern Area Reduction with 3 Dimensional Transistor for Logic Circuit
Yu HIROSHIMA Takahiro KODAMA Shigeyoshi WATANABE
C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date: 2011/10/01
Online ISSN: 1881-0217
Print ISSN: 1345-2827
Type of Manuscript: LETTER
FinFET, double gate transistor, stacked type transistor, full added, pattern area,
Full Text(in Japanese): PDF(465.9KB)
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Pattern area reduction with 3 dimensional transistor and various kind of circuit scheme for logic circuit such as full adder has been newly studied. Pattern area reduction ratio with 3 dimensional transistor is large for full adder consisted with large number of transistor. In the case for full adder consisted with small number of transistor, the pattern area reduction ratio is relatively small.