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Study of Pattern Area Reduction for System LSI with SGT and Stacked SGT
Takahiro KODAMA Shigeyoshi WATANABE
C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date: 2010/01/01
Online ISSN: 1881-0217
Print ISSN: 1345-2827
Type of Manuscript: LETTER
SGT, stacked SGT, system LSI, design rule, pattern area,
Full Text(in Japanese): PDF(415.5KB)
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Pattern area reduction with stacked SGT for logic circuit such as inverter and NAND gates and full adder has been newly investigated. Pattern area reduction of logic circuit is enhanced by reduction of number of input and channel width.