Application Design of Multi-Standard Decoder on Media-Centric Reconfigurable Architecture

Yukio MITSUYAMA  Kazuma TAKAHASHI  Rintaro IMAI  Masanori HASHIMOTO  Takao ONOYE  Isao SHIRAKAWA 

Publication
A - Abstracts of IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (Japanese Edition)  Vol.J93-A  No.6  pp.397-413
Publication Date: 2010/06/01
Online ISSN: 1881-0195
Print ISSN: 0913-5707
Type of Manuscript: PAPER
Category: 
Keyword: 
reconfigurable architecture,  mapping,  video decoder,  pixel-parallelism, 

Full Text(in Japanese): PDF(1.6MB)

Summary: 
An application design of multi-standard video decoder is described by exploiting high area-efficiency of a heterogeneous coarse-grained reconfigurable architecture, which can decode MPEG-2 MP@ML, MPEG-4 simple profile, and H.263 baseline profile. Based on macro-cells, each of which is constructed by combination of heterogeneous functional cells and offers basic function needed for media processing, a series of decoding processes are successfully implemented. Performance enhancement by aggressive utilization of the scalability of the reconfigurable architecture and functional extension to implement an uniform polyphase filter bank are also explained.