Development of Full-Stacked Via Printed Wiring Board with High Thermal Reliability

Akihiko HAPPOYA  Akira TANAKA  Kenji HIROHATA  Shun OKAYAMA 

Publication
C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)  Vol.J92-C  No.11  pp.703-711
Publication Date: 2009/11/01
Online ISSN: 1881-0217
Print ISSN: 1345-2827
Type of Manuscript: Special Section PAPER (Special Issue on Advanced Packging and Environmentally Conscious Packaging Technologies in Next-Generation Electronic Equipment)
Category: 
Keyword: 
printed wiring board,  thermal stress,  reliability,  stacked via,  halogen-free, 

Full Text(in Japanese): PDF(1.7MB)

Summary: 
For two different types of stacked via printed wiring boards, one made of filled copper plated layers only, and the other one made of a combination of filled copper plated layers and silver paste bumps, a thermal stress cycle testing and FEM analysis was made for demonstrating the effect of the via structure and dielectric material on via's electrical connection reliability. As a result, the latter via structure, i.e. that consisting of a combination of filled copper plated layers and silver paste bumps, associated with the halogen-free FR 4 substrate were found to show highest thermal stress reliability.