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Through-Silicon Via Interconnection for 3D Integration Using Room-Temperature Bonding
C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition) Vol.J91-C No.11 pp.542-551
Publication Date: 2008/11/01
Online ISSN: 1881-0217
Print ISSN: 1345-2827
Type of Manuscript: Special Section PAPER (Special Issue on Leading-Edge Trend of Advanced Packages for Electron Devices and Its Related Topics for High-Density Packaging Process Technologies)
through silicon via (TSV),
room temperature bonding,
Full Text(in Japanese): PDF(2.4MB)
One approach to 3D technology is chip stacking using through-silicon via (TSV). Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for faster system speed and lower power consumption. However, it is extremely important to use cost-effective process technologies in practical use. Therefore, in our study, we propose a basic concept for interconnecting stacked chips with TSVs using a cost-effective process technology. The principal feature is to use a "mechanical-caulking" technique, which has been used widely in the mechanical-engineering field, enabling 3D interconnections between stacked chips. This makes it possible to interconnect them by only applying compressive force at room temperature.