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Dynamic Reconfigurable Variable-Length Processor Core with 30 fr/s HDTV to H.264, MPEG-2 and MPEG-4
D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Vol.J89-D No.6 pp.1091-1100
Publication Date: 2006/06/01
Online ISSN: 1881-0225
Print ISSN: 1880-4535
Type of Manuscript: Special Section PAPER (Special Issue Reconfigurable Systems)
dynamic reconfigurable hardware,
variable length code,
Full Text(in Japanese): PDF(1.5MB)
A dynamic reconfigurable variable-length codec processor core that complies with various video codec standards is described herein. This core meets such standards as H.264, MPEG-2, and MPEG-4. It achieves realtime encoding and decoding for QCIF, CIF, NTSC, for H.264 standard and HDTV-resolution for MPEG-2 at a frame rate of 30 fr/s. The core consists of a dynamic reconfigurable variable-length code table, a bitstream feeder, a bitstream compactor, two memories for storing bitstream and coefficient data, and control logic. We divided the bit comparison width and applied dynamic reconfigurable logic composed of a 45 cell element array and control logic to minimize the size of the variable-length codec hardware and retain compatibility with the completely different code lengths of those various standards. Each cell element has a 4-bit-width function cell for code comparison and a joint cell that transmits coincident signals to the function cell and neighboring cell elements. Embedded in each cell are four configuration information registers. A dynamic reconfiguration is achieved by changing the register select signal. A single clock dynamic reconfiguration by changing register select signal enables this core to accomplish real-time encoding and decoding for MPEG-2 HDTV-resolution video at a 30 fr/s frame rate. This core was designed with six-metal 0.18-µm CMOS technology to produce a chip area of 1.11.1 mm2.