Evaluation of Temperature Dependence of Local Stress and CMOS Circuit Properties in Three-Dimensional LSI Design

Shoichi MIYAHARA  Hideki KITADA  Hiroko TASHIRO  Aki DOTE  Seiki SAKUYAMA  

Publication
C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)   Vol.J101-C   No.2   pp.74-82
Publication Date: 2018/02/01
Online ISSN: 1881-0217
Type of Manuscript: Special Section PAPER (Special Section on Heterogeneous Integration Packaging Technologies Realizing Next Generation Mobility Devices)
Category: 
Keyword: 
3D-LSI,  CMOS property,  TSV stress,  temperature dependence,  

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Summary: 
An impact of local stress induced by TSV in various thermal conditions on CMOS circuit are analyzed using the circuit model (SPICE) generated by the stress-device simulator (TCAD), and compared with measured thermal property of 3D-LSI. We propose the new method to estimate a Keep-Out Zone (KOZ) precisely by measuring the thermal coefficients of delay time of CMOS ring oscillators. With this measurements, we could successfully detect an impact of the stress of different 3D stacking structures on package. This method is beneficial to establish the circuit design system for large scale 3D-LSI including packages.