For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Pseudo-CMOS with Re-Pull-Down Transistor: A Low Power Inverter Design for Thin-Film Transistors
Lihao ZHONG Ruohe YAO Fei LUO
IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Online ISSN: 1745-1353
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
Pseudo-CMOS, low power, re-pull-down, thin-film transistor,
Full Text: PDF(374.7KB)>>
In order to further optimize the power consumption of Pseudo-CMOS inverter, this paper proposes a Re-Pull-Down transistor scheme. Two additional transistors are used to build another pull-down network. With this design, the quiescent current of the inverter can be reduced while the ratioless nature is preserved. Based on the reduced input gate area, two output transistors are set wider to compensate for the pull-up speed. The simulation result shows that, compared with Pseudo-CMOS inverter, the maximum quiescent current of the Re-Pull-Down transistor scheme inverter is reduced by 37.6% in the static analysis. Besides, the average power consumption is reduced by 30.8% in the 5-stage ring oscillator test.