RSFQ 4-bit Bit-Slice Integer Multiplier

Guang-Ming TANG  Kazuyoshi TAKAGI  Naofumi TAKAGI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.6   pp.697-702
Publication Date: 2016/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.697
Type of Manuscript: Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
Category: 
Keyword: 
multiplier,  single-flux-quantum (SFQ),  microprocessor,  superconducting integrated circuits,  

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Summary: 
A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-µm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n×4n-bit multiplier consists of 2n+17 stages. For verifying the algorithm and the logic design, a physical layout of the 8×8-bit multiplier has been designed with target operating frequency of 50GHz and simulated. It consists of 21 stages and 11,488 Josephson junctions. The simulation results show correct operation up to 62.5GHz.