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An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter
Keisuke OKUNO Toshihiro KONISHI Shintaro IZUMI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI
IEICE TRANSACTIONS on Electronics
Publication Date: 2015/06/01
Online ISSN: 1745-1353
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
ADC, I/O-size, VTC, MOM capacitance,
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We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal–oxide–metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm2 and 509 μW. The measured maximum integral nonlinearity (INL) of the proposed ADC is -1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.