An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology

Shoichiro KAWASHIMA  Keizo MORITA  Mitsuharu NAKAZAWA  Kazuaki YAMANE  Mitsuhiro OGAI  Kuninori KAWABATA  Kazuaki TAKAI  Yasuhiro FUJII  Ryoji YASUDA  Wensheng WANG  Yukinobu HIKOSAKA  Ken'ichi INOUE  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E98-C   No.11   pp.1047-1057
Publication Date: 2015/11/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E98.C.1047
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
1T1C-FeRAM,  sectional cyclic word line,  bit-line GND level sensing,  planar FeRAM cell,  temperature-bit distribution,  

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Summary: 
An 8-Mbit 0.18-µm CMOS 1T1C ferroelectric RAM (FeRAM) in a planar ferroelectric technology was developed. Even though the cell area of 2.48 µm2 is almost equal to that of a 4-Mbit stacked-capacitor FeRAM (STACK FeRAM) 2.32 µm2[1], the chip size of the developed 8-Mbit FeRAM, including extra 2-Mbit parities for the error correction code (ECC), is just 52.37 mm2, which is about 30% smaller than twice of the 4-Mbit STACK FeRAM device, 37.68mm2×2[1]. This excellent characteristic can be attributed to the large cell matrix architectures of the sectional cyclic word line (WL) that was used to increase the column numbers, and to the 1T1C bit-line GND level sensing (BGS)[2][3] circuit design intended to sense bit lines (BL) that have bit cells 1K long and a large capacitance. An access time of 52 ns and a cycle time of 77 ns in RT at a VDD of 1.8 V were achieved.