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Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network
Xu BAI Michitaka KAMEYAMA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Online ISSN: 1745-1361
Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
multiple-valued reconfigurable VLSI, fine-grain reconfigurable VLSI, global tree local X-net network, logic-in-memory architecture,
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A global tree local X-net network (GTLX) is introduced to realize high-performance data transfer in a multiple-valued fine-grain reconfigurable VLSI (MVFG-RVLSI). A global pipelined tree network is utilized to realize high-performance long-distance bit-parallel data transfer. Moreover, a logic-in-memory architecture is employed for solving data transfer bottleneck between a block data memory and a cell. A local X-net network is utilized to realize simple interconnections and compact switch blocks for eight-near neighborhood data transfer. Moreover, multiple-valued signaling is utilized to improve the utilization of the X-net network, where two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each “X” intersection. To evaluate the MVFG-RVLSI, a fast Fourier transform (FFT) operation is mapped onto a previous MVFG-RVLSI using only the X-net network and the MVFG-RVLSI using the GTLX. As a result, the computation time, the power consumption and the transistor count of the MVFG-RVLSI using the GTLX are reduced by 25%, 36% and 56%, respectively, in comparison with those of the MVFG-RVLSI using only the X-net network.