Formal Design of Arithmetic Circuits over Galois Fields Based on Normal Basis Representations

Kotaro OKAMOTO  Naofumi HOMMA  Takafumi AOKI  

IEICE TRANSACTIONS on Information and Systems   Vol.E97-D   No.9   pp.2270-2277
Publication Date: 2014/09/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2013LOP0012
Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
arithmetic circuits,  formal verification,  normal basis,  computer algebra,  

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This paper presents a graph-based approach to designing arithmetic circuits over Galois fields (GFs) using normal basis representations. The proposed method is based on a graph-based circuit description called Galois-field Arithmetic Circuit Graph (GF-ACG). First, we extend GF-ACG representation to describe GFs defined by normal basis in addition to polynomial basis. We then apply the extended design method to Massey-Omura parallel multipliers which are well known as typical multipliers based on normal basis. We present the formal description of the multipliers in a hierarchical manner and show that the verification time can be greatly reduced in comparison with those of the conventional techniques. In addition, we design GF exponentiation circuits consisting of the Massey-Omura parallel multipliers and an inversion circuit over composite field GF(((22)2)2) in order to demonstrate the advantages of normal-basis circuits over polynomial-basis ones.