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A Lower Bound on the Gate Count of ToffoliBased Reversible Logic Circuits
Takashi HIRAYAMA Hayato SUGAWARA Katsuhisa YAMANAKA Yasuaki NISHITANI
Publication
IEICE TRANSACTIONS on Information and Systems
Vol.E97D
No.9
pp.22532261 Publication Date: 2014/09/01
Online ISSN: 17451361
DOI: 10.1587/transinf.2013LOP0013
Type of Manuscript: Special Section PAPER (Special Section on MultipleValued Logic and VLSI Computing) Category: Reversible/Quantum Computing Keyword: reversible logic circuits, Toffoli gates, lower bound, logic minimization,
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Summary:
We present a new lower bound on the number of gates in reversible logic circuits that represent a given reversible logic function, in which the circuits are assumed to consist of general Toffoli gates and have no redundant input/output lines. We make a theoretical comparison of lower bounds, and prove that the proposed bound is better than the previous one. Moreover, experimental results for lower bounds on randomlygenerated reversible logic functions and reversible benchmarks are given. The results also demonstrate that the proposed lower bound is better than the former one.

