Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm

Rompei SUGAWARA  Hao SAN  Kazuyuki AIHARA  Masao HOTTA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.4   pp.308-315
Publication Date: 2014/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.308
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
Non-binary ADC,  Cyclic ADC,  Radix value estimation algorithm,  β expansion,  Multiply-by-β MDAC,  

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Summary: 
Proof-of-concept cyclic analog-to-digital converters (ADCs) have been designed and fabricated in 90-nm CMOS technology. The measurement results of an experimental prototype demonstrate the effectiveness of the proposed switched-capacitor (SC) architecture to realize a non-binary ADC based on β expansion. Different from the conventional binary ADC, a simple 1-bit/step structure for an SC multiplying digital-to-analog converter (MDAC) is proposed to present residue amplification by β (1 < β < 2). The redundancy of non-binary ADCs with radix β tolerates the non-linear conversion errors caused by the offsets of comparators, the mismatches of capacitors, and the finite DC gains of amplifiers, which are used in the MDAC. We also employed a radix value estimation algorithm to obtain an effective value of β for non-binary encoding; it can be realized by merely adding a simple conversion sequence and digital circuits. As a result, the power penalty of a high-gain wideband amplifier and the required accuracy of the circuit elements for a high-resolution ADC were largely relaxed so that the circuit design was greatly simplified. The implemented ADC achieves a measured peak signal-to-noise-and-distortion-ratio (SNDR) of 60.44dB, even with an op-amp with a poor DC gain (< 50dB) while dissipating 780µW in analog circuits at 1.4V and occupying an active area of 0.25 × 0.26mm2.