Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process

Xizhu PENG  Yuki YAMANASHI  Nobuyuki YOSHIKAWA  Akira FUJIMAKI  Naofumi TAKAGI  Kazuyoshi TAKAGI  Mutsuo HIDAKA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.3   pp.188-193
Publication Date: 2014/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.188
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
floating point unit,  multiplier,  LSRDP,  SFQ circuit,  superconductive integrated circuit,  

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Summary: 
Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.