For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits
Shih-Hsu HUANG Hua-Hsin YEH
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/08/01
Online ISSN: 1745-1337
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
electronic design automation, high-level design stage, design partitioning, layer assignment, three-dimensional integrated circuits, temperature increase,
Full Text: PDF(4.5MB)
>>Buy this Article
Because dielectrics between active layers have low thermal conductivities, there is a demand to reduce the temperature increase in three-dimensional integrated circuits (3D ICs). This paper demonstrates that, in the design of 3D ICs, different layer assignments often lead to different temperature increases. Based on this observation, we are motivated to perform temperature-aware layer assignment. Our work includes two parts. Firstly, an integer linear programming (ILP) approach that guarantees a minimum temperature increase is proposed. Secondly, a polynomial-time heuristic algorithm that reduces the temperature increase is proposed. Compared with the previous work, which does not take the temperature increase into account, the experimental results show that both our ILP approach and our heuristic algorithm produce a significant reduction in the temperature increase with a very small area overhead.