Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication

Nobutaka KITO  Naofumi TAKAGI  

IEICE TRANSACTIONS on Information and Systems   Vol.E96-D   No.9   pp.1962-1970
Publication Date: 2013/09/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E96.D.1962
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Dependable Computing)
parity prediction,  parallel prefix adder,  fault secure,  carry-bit duplication,  

Full Text: PDF(968.9KB)
>>Buy this Article

We propose a low-overhead fault-secure parallel prefix adder. We duplicate carry bits for checking purposes. Only one half of normal carry bits are compared with the corresponding redundant carry bits, and the hardware overhead of the adder is low. For concurrent error detection, we also predict the parity of the result. The adder uses parity-based error detection and it has high compatibility with systems that have parity-based error detection. We can implement various fault-secure parallel prefix adders such as Sklansky adder, Brent-Kung adder, Han-Carlson adder, and Kogge-Stone adder. The area overhead of the proposed adder is about 15% lower than that of a previously proposed adder that compares all the carry bits.