For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Online ISSN: 1745-1361
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)
FPGA, reconfigurable LSI, self-timed circuit, asynchronous circuit,
Full Text: PDF(3.8MB)>>
This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshake-component-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an area-efficient architecture of an FPGA that is suitable for handshake-component-based asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.