Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption

Yohei HORI  Toshihiro KATASHITA  Hirofumi SAKANE  Kenji TODA  Akashi SATOH  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E96-D   No.11   pp.2333-2343
Publication Date: 2013/11/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E96.D.2333
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
Keyword: 
dynamic partial reconfiguration (DPR),  field-programmable gate array (FPGA),  Advanced Encryption Standard (AES),  Galois/Counter Mode (GCM),  authenticated encryption,  

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Summary: 
Protecting the confidentiality and integrity of a configuration bitstream is essential for the dynamic partial reconfiguration (DPR) of field-programmable gate arrays (FPGAs). This is because erroneous or falsified bitstreams can cause fatal damage to FPGAs. In this paper, we present a high-speed and area-efficient bitstream protection scheme for DPR systems using the Advanced Encryption Standard with Galois/Counter Mode (AES-GCM), which is an authenticated encryption algorithm. Unlike many previous studies, our bitstream protection scheme also provides a mechanism for error recovery and tamper resistance against configuration block deletion, insertion, and disorder. The implementation and evaluation results show that our DPR scheme achieves a higher performance, in terms of speed and area, than previous methods.