1.5–9.7-Gb/s Complete 4-PAM Serial Link Transceiver with a Wide Frequency Range CDR

Bongsub SONG  Kyunghoon KIM  Junan LEE  Kwangsoo KIM  Younglok KIM  Jinwook BURM  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.8   pp.1048-1053
Publication Date: 2013/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.1048
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
high-speed integrated circuits,  pulse-amplitude modulation (PAM),  serial-link,  clock data recovery (CDR),  

Full Text: PDF(3.4MB)>>
Buy this Article




Summary: 
A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5 Gb/s to 9.7 Gb/s with a bit error rate of 10-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254 mW, and the measured jitter of the recovered clock is 1.61 psrms.