Robust Cyclic ADC Architecture Based on β-Expansion

Rie SUZUKI  Tsubasa MARUYAMA  Hao SAN  Kazuyuki AIHARA  Masao HOTTA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E96-C   No.4   pp.553-559
Publication Date: 2013/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.553
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
robust ADC,  β-expansion,  redundancy,  cyclic ADC,  radix-value estimation algorithm,  

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Summary: 
In this paper, a robust cyclic ADC architecture with β-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wideband amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90 nm. We also propose a β-value estimation algorithm to realize high accuracy ADC based on β-expansion. The simulation results show the effectiveness of proposed architecture and robustness of β-encoder.